/* E18RC-MW500-N MIPI TFT Display Driver File
   Created on June 2, 2026, 12:15 PM

   @Company
	 Focus LCDs
	 LCDs Made Simple
	 www.focuslcds.com

   @File Name
	 E18RC-MW500-N_1-Lane-MIPI-CODE.txt

   @Summary
	 This is the driver source file for the TFT Display
	 Display:         1.8" TFT LCD 240 x 320
	 Controller Chip: JD9852
	 Interface:       1-Lane MIPI
	 MCU/MPU:         Generic

   @Version
	 Version 1.0.0 (Semantic Versioning 2.0.0)

   @Description
	 This source file provides initialization for the 1.8" TFT display.
*/
/*******************************************************************************/

/*******************************************************************************
	(c) 2023 Focus LCDs and its subsidiaries. You may use this software and any
	derivatives exclusively with Focus LCDs products.

	THIS SOFTWARE IS SUPPLIED BY FOCUS LCDS "AS IS". NO WARRANTIES, WHETHER
	EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED
	WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
	PARTICULAR PURPOSE, OR ITS INTERACTION WITH FOCUS LCDS PRODUCTS, COMBINATION
	WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION.

	IN NO EVENT WILL FOCUS LCDS BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE,
	INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND
	WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF FOCUS LCDS HAS
	BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE
	FULLEST EXTENT ALLOWED BY LAW, FOCUS LCDS' TOTAL LIABILITY ON ALL CLAIMS IN
	ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
	THAT YOU HAVE PAID DIRECTLY TO FOCUSLCDS FOR THIS SOFTWARE.

	FOCUS LCDS PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE
	TERMS.
*******************************************************************************/



JDEVB_IF(DSI_VDO);		//DSI_interface
JDEVB_RSOX(240);    
JDEVB_RSOY(320);    
JDEVB_VS(2);
JDEVB_VBP(6);
JDEVB_VFP(8);    
JDEVB_HS(4);
JDEVB_HBP(20);
JDEVB_HFP(40); 
JDEVB_DSILANE(1);	//DSI Lane
JDEVB_DOTCLK(6.2);// MHZ  PCLK
params->dsi.PLL_CLOCK=(70)//MTK  Mbps
params->MIPI_CLOCK=(150)Mbps
Frame Rate=60HZ
JDEVB_IOVCC(1.8);    //SSD_IOVCC Power 
JDEVB_VCI(2.8-3.3);  //VCI Power
Compare ID Register:page0 R04H=[0x98,0x52] 
//********************************************
void initi(void)
{
   res=1;
   delay(1);//MS
   res=0;
   delay(10);//MS
   res=1;
   delay(120);//MS
///***************************//
SSD_CMD(0xDF); //Password
SSD_PAR(0x98);
SSD_PAR(0x51);
SSD_PAR(0xE9);

//---------------- PAGE0 --------------

SSD_CMD(0xDE);  	
SSD_PAR(0x00);  

//VGMP,VGSP,VGMN,VGSN 
SSD_CMD(0xB7);// 	
SSD_PAR(0x5F);//
SSD_PAR(0x90);//
SSD_PAR(0x35);//
SSD_PAR(0x0C);//

//Set_R_GAMMA
SSD_CMD(0xC8); 	
SSD_PAR(0x3F);//   	
SSD_PAR(0x36);// 
SSD_PAR(0x2F);// 
SSD_PAR(0x2C);// 
SSD_PAR(0x31);// 
SSD_PAR(0x3A);// 
SSD_PAR(0x39);// 
SSD_PAR(0x3B);// 
SSD_PAR(0x3D);// 
SSD_PAR(0x3E);// 
SSD_PAR(0x3F);// 
SSD_PAR(0x3C);// 
SSD_PAR(0x38);// 
SSD_PAR(0x2E);// 
SSD_PAR(0x26);// 
SSD_PAR(0x0E);// 
SSD_PAR(0x3F);//   	
SSD_PAR(0x36);// 
SSD_PAR(0x2F);// 
SSD_PAR(0x2C);// 
SSD_PAR(0x32);// 
SSD_PAR(0x39);// 
SSD_PAR(0x39);// 
SSD_PAR(0x3B);// 
SSD_PAR(0x3D);// 
SSD_PAR(0x3E);// 
SSD_PAR(0x3F);// 
SSD_PAR(0x3C);// 
SSD_PAR(0x38);// 
SSD_PAR(0x2E);// 
SSD_PAR(0x26);// 
SSD_PAR(0x0E);// 

//POW_CTRL
SSD_CMD(0xB9);  	
SSD_PAR(0x33);	   	
SSD_PAR(0x08);
SSD_PAR(0xCC);

//DCDC_SEL 

SSD_CMD(0xBB);  	
SSD_PAR(0x00);//VGH 11.15,VGL-7 	
SSD_PAR(0x7A);
SSD_PAR(0x40);  	
SSD_PAR(0xD0); //3 	
SSD_PAR(0x7C); //6 	
SSD_PAR(0x60);  	
SSD_PAR(0x50);//50  	
SSD_PAR(0x70);

//VDDD_CTRL 
SSD_CMD(0xBC);  	
SSD_PAR(0x38);  	
SSD_PAR(0x3C);

//SETSTBA
SSD_CMD(0xC0);
SSD_PAR(0x31);
SSD_PAR(0x20);

//SETPANEL(default)  
SSD_CMD(0xC1);  	
SSD_PAR(0x12); 

//SETRGBCYC 
SSD_CMD(0xC3);  	
SSD_PAR(0x08);
SSD_PAR(0x00);  	
SSD_PAR(0x0A);
SSD_PAR(0x10);  	
SSD_PAR(0x08);  	
SSD_PAR(0x54);  	
SSD_PAR(0x45);  	
SSD_PAR(0x71);  	
SSD_PAR(0x2C);

//SETRGBCYC(default)  
SSD_CMD(0xC4);  	
SSD_PAR(0x00);
SSD_PAR(0xA0);  	
SSD_PAR(0x79);
SSD_PAR(0x0E);  	
SSD_PAR(0x0A);  	
SSD_PAR(0x16);  	
SSD_PAR(0x79);  	
SSD_PAR(0x0E);  	
SSD_PAR(0x0A);
SSD_PAR(0x16);  	
SSD_PAR(0x79);  	
SSD_PAR(0x0E);  	
SSD_PAR(0x0A);  	
SSD_PAR(0x16);  	
SSD_PAR(0x82);  	
SSD_PAR(0x00);  	
SSD_PAR(0x03);


//SET_GD(default)
SSD_CMD(0xD0);  	
SSD_PAR(0x04);
SSD_PAR(0x0C);  	
SSD_PAR(0x6B);
SSD_PAR(0x0F);  	
SSD_PAR(0x07);  	
SSD_PAR(0x03);

//RAMCTRL(default)

SSD_CMD(0xD7);  	
SSD_PAR(0x13);
SSD_PAR(0x00);  

//---------------- PAGE2 --------------

SSD_CMD(0xDE);  	
SSD_PAR(0x02);  
Delayms(1);

//DCDC_SET

SSD_CMD(0xB8);  	
SSD_PAR(0x1D);
SSD_PAR(0xA0);
SSD_PAR(0x2F);
SSD_PAR(0x24);
SSD_PAR(0x28);

//SETRGBCYC2

SSD_CMD(0xC1);  	
SSD_PAR(0x10);
SSD_PAR(0x66);
SSD_PAR(0x66);
SSD_PAR(0x01);

//---------------- PAGE0 --------------

SSD_CMD(0xDE);  	
SSD_PAR(0x00);  


// sleep out

SSD_CMD(0x11);  	// SLPOUT
Delayms(120);


//---------------- PAGE2 --------------

SSD_CMD(0xDE);  	
SSD_PAR(0x02);  
Delayms(1);

//OSCM

SSD_CMD(0xC5);  	
SSD_PAR(0x4E); 	
SSD_PAR(0x00);
SSD_PAR(0x00);
Delayms(1);

//SETMIPI_2

SSD_CMD(0xCA);  	
SSD_PAR(0x30); 	
SSD_PAR(0x20);
SSD_PAR(0xF4);
Delayms(1);

//---------------- PAGE4 --------------

SSD_CMD(0xDE);  	
SSD_PAR(0x04);  
Delayms(1);

//SETPHY3

SSD_CMD(0xD3);  	
SSD_PAR(0x3C);  
Delayms(1);
//---------------- PAGE0 --------------

SSD_CMD(0xDE);  	
SSD_PAR(0x00);
Delayms(1);  

// display on

SSD_CMD(0x29);  	// SLPOUT

}
//*******************************************
void EnterSleep (void)
{
    write_command(0x28);
    delay(10);
    write_command(0x10);
  
  }

//*********************************************************
void ExitSleep (void)

 {
    write_command(0x11);
    delay(120);
    write_command(0x29);

   }