/* E35RJ-I-MS450-CB MIPI DSI TFT Display Driver File Created on February 5, 2026, 1:22 PM @Company Focus LCDs LCDs Made Simple www.focuslcds.com @File Name E35RJ-I-MS450-CB-2LANE-MIPI-CODE.txt @Summary This is the driver source file for the TFT Display Display: 3.5" TFT LCD 640 x 960 Controller Chip: ST7703 Interface: MIPI DSI 2-Lane MCU/MPU: Generic @Version Version 1.0.0 (Semantic Versioning 2.0.0) @Description This source file provides initialization for the 3.5" TFT display. */ /*******************************************************************************/ /******************************************************************************* (c) 2023 Focus LCDs and its subsidiaries. You may use this software and any derivatives exclusively with Focus LCDs products. THIS SOFTWARE IS SUPPLIED BY FOCUS LCDS "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR ITS INTERACTION WITH FOCUS LCDS PRODUCTS, COMBINATION WITH ANY OTHER PRODUCTS, OR USE IN ANY APPLICATION. IN NO EVENT WILL FOCUS LCDS BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF FOCUS LCDS HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, FOCUS LCDS' TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO FOCUSLCDS FOR THIS SOFTWARE. FOCUS LCDS PROVIDES THIS SOFTWARE CONDITIONALLY UPON YOUR ACCEPTANCE OF THESE TERMS. *******************************************************************************/ /* Display resolution:640*960 params->dsi.vertical_sync_active=4 params->dsi.vertical_backporch=12 params->dsi.vertical_frontporch=16 params->dsi.horizontal_sync_active=4 params->dsi.horizontal_backporch=20 params->dsi.horizontal_frontporch=8 params->RGB_CLOCK=(40)M Frame Rate=60HZ /**********************LCD***************************/ void initi(void) { res=1; delay(1); res=0; delay(10); res=1; delay(120); //**************************************//LCD SETTING write_command(0xB9); /// Set EXTC write_data(0xF1); //1 write_data(0x12); //2 write_data(0x83); //3 write_command(0xB2); /// Set RSO write_data(0x78); //1 720*672 write_data(0x23); //2 write_data(0xF0); //3 write_command(0xB3); /// SET RGB write_data(0x10); //1 VBP_RGB_GEN 7 write_data(0x10); //2 VFP_RGB_GEN 0B write_data(0x28); //3 DE_BP_RGB_GEN 1E write_data(0x28); //4 DE_FP_RGB_GEN 1E write_data(0x03); //5 write_data(0xFF); //6 write_data(0x00); //7 write_data(0x00); //8 write_data(0x00); //9 write_data(0x00); //10 write_command(0xB4); /// Set Panel Inversion write_data(0x80); //1 write_command(0xB5); /// Set BGP write_data(0x0A); //1 vref write_data(0x0A); //2 nvref write_command(0xB6); /// Set VCOM //2024.09.27 write_data(0xD0); //1 F_VCOM write_data(0xD0); //2 B_VCOM write_command(0xB8); ///Set ECP write_data(0x25); /0x25 for Power IC Mode write_data(0x22); write_data(0xF0); write_data(0x63); write_command(0xBA); /// Set DSI write_data(0x31); //1 //33:4Lane,32:3Lane,31:2Lane write_data(0x81); //2 write_data(0x05); //3 write_data(0xF9); //4 write_data(0x0E); //5 write_data(0x0E); //6 write_data(0x20); //7 write_data(0x00); //8 write_data(0x00); //9 write_data(0x00); //10 write_data(0x00); //11 write_data(0x00); //12 write_data(0x00); //13 write_data(0x00); //14 write_data(0x44); //15 write_data(0x25); //16 write_data(0x00); //17 write_data(0x90); //18 write_data(0x0A); //19 write_data(0x00); //20 write_data(0x00); //21 write_data(0x01); //22 write_data(0x4F); //23 write_data(0x01); //24 write_data(0x00); //25 write_data(0x00); //26 write_data(0x37); //27 write_command(0xBC); /// Set VDC write_data(0x46); //1 default=46 write_command(0xBF); ///Set PCR write_data(0x02); // write_data(0x11); write_data(0x00); write_command(0xC0); /// Set SCR write_data(0x73); //1 write_data(0x73); //2 write_data(0x50); //3 write_data(0x50); //4 write_data(0x00); //5 write_data(0x00); //6 write_data(0x08); //7 write_data(0x70); //8 write_data(0x00); //9 write_command(0xC1); /// Set POWER //2024.09.27 write_data(0x25); //1 VBTHS VBTLS write_data(0xC0); //2 E3 write_data(0x32); //3 VSPR write_data(0x32); //4 VSNR write_data(0x99); //5 VSP VSN write_data(0xE4); //6 APS write_data(0xFF); //7 VGH1 VGL1 write_data(0xFF); //8 VGH1 VGL1 write_data(0xCC); //9 VGH2 VGL2 write_data(0xCC); //10 VGH2 VGL2 write_data(0x77); //11 VGH3 VGL3 write_data(0x77); //12 VGH3 VGL3 write_command(0xC6); /// Set SCR write_data(0x82); //1 write_data(0x00); //2 write_data(0x3F); //3 write_data(0xFF); //4 write_data(0x00); //5 write_data(0xE0); //6 write_command(0xCC); /// Set Panel write_data(0x0B); //1 Forward:0x0B , Backward:0x07 write_command(0xE0); /// Set Gamma write_data(0x00); //1 write_data(0x29); //2 write_data(0x2C); //3 write_data(0x2F); //4 write_data(0x3E); //5 write_data(0x3F); //6 write_data(0x53); //7 write_data(0x3E); //8 write_data(0x08); //9 write_data(0x0D); //10 write_data(0x0D); //11 write_data(0x11); //12 write_data(0x13); //13 write_data(0x11); //14 write_data(0x13); //15 write_data(0x0E); //16 write_data(0x18); //17 write_data(0x00); //18 write_data(0x29); //19 write_data(0x2C); //20 write_data(0x2F); //21 write_data(0x3E); //22 write_data(0x3F); //23 write_data(0x53); //24 write_data(0x3E); //25 write_data(0x08); //26 write_data(0x0D); //27 write_data(0x0D); //28 write_data(0x11); //29 write_data(0x13); //30 write_data(0x11); //31 write_data(0x13); //32 write_data(0x0E); //33 write_data(0x18); //34 write_command(0xE3); /// Set EQ write_data(0x07); //1 PNOEQ write_data(0x07); //2 NNOEQ write_data(0x0B); //3 PEQGND write_data(0x0B); //4 NEQGND write_data(0x03); //5 PEQVCI write_data(0x0B); //6 NEQVCI write_data(0x00); //7 PEQVCI1 write_data(0x00); //8 NEQVCI1 write_data(0x00); //9 VCOM_PULLGND_OFF write_data(0x00); //10 VCOM_PULLGND_OFF write_data(0xFF); //11 VCOM_IDLE_ON write_data(0x00); //12 EACH_OPON=0 write_data(0xC0); //13 default C0 ESD detect function write_data(0x10); //14 SLPOTP write_command(0xE9); /// Set GIP write_data(0xC1); //1 PANSEL //02,C2 write_data(0x10); //2 SHR_0[11:8] //00,10 write_data(0x0A); //3 SHR_0[7:0] //03,0B write_data(0x03); //4 SHR_1[11:8] //04,04 write_data(0xC4); //5 SHR_1[7:0] //4B,3F for GCH write_data(0xA1); //6 SPON[7:0] write_data(0x80); //7 SPOFF[7:0] write_data(0x12); //8 SHR0_1[3:0], SHR0_2[3:0] write_data(0x31); //9 SHR0_3[3:0], SHR1_1[3:0] write_data(0x23); //10 SHR1_2[3:0], SHR1_3[3:0] write_data(0x47); //11 SHP[3:0], SCP[3:0] write_data(0x86); //12 CHR[7:0] //07,86 write_data(0xA1); //13 CON[7:0] E1 write_data(0x80); //14 COFF[7:0] C0 write_data(0x47); //15 CHP[3:0], CCP[3:0] write_data(0x08); //16 USER_GIP_GATE[7:0] write_data(0x30); //17 CGTS_L[21:16] write_data(0x00); //18 CGTS_L[15:8] write_data(0x80); //19 CGTS_L[7:0] write_data(0x00); //20 CGTS_INV_L[21:16] write_data(0x00); //21 CGTS_INV_L[15:8] write_data(0x00); //22 CGTS_INV_L[7:0] write_data(0x30); //23 CGTS_R[21:16] write_data(0x00); //24 CGTS_R[15:8] write_data(0x80); //25 CGTS_R[7:0] write_data(0x00); //26 CGTS_INV_R[21:16] write_data(0x00); //27 CGTS_INV_R[15:8] write_data(0x00); //28 CGTS_INV_R[7:0] write_data(0x88); //29 COS1_L[3:0], COS2_L[3:0] ,// VSD write_data(0x8F); //30 COS3_L[3:0], COS4_L[3:0] ,// VSD VDS write_data(0xF8); //31 COS5_L[3:0], COS6_L[3:0] ,// VDS GCL write_data(0x84); //32 COS7_L[3:0], COS8_L[3:0] ,// GCL STV0_R write_data(0x44); //33 COS9_L[3:0], COS10_L[3:0],// CLK1 CLK1 write_data(0x66); //34 COS11_L[3:0], COS12_L[3:0],// CLK3 CLK3 write_data(0x00); //35 COS13_L[3:0], COS14_L[3:0],// CLK5 CLK5 write_data(0x22); //36 COS15_L[3:0], COS16_L[3:0],// CLK7 CLK7 write_data(0x88); //37 COS17_L[3:0], COS18_L[3:0],// VGL VGL write_data(0xFF); //38 COS19_L[3:0], COS20_L[3:0],// GCH GCH write_data(0x02); //39 COS21_L[3:0], COS22_L[3:0],// STV1 STV3 write_data(0x88); //40 COS1_R[3:0], COS2_R[3:0] ,// write_data(0x8F); //41 COS3_R[3:0], COS4_R[3:0] ,// write_data(0xF8); //42 COS5_R[3:0], COS6_R[3:0] ,// write_data(0x85); //43 COS7_R[3:0], COS8_R[3:0] ,// write_data(0x55); //44 COS9_R[3:0], COS10_R[3:0],// write_data(0x77); //45 COS11_R[3:0], COS12_R[3:0],// write_data(0x11); //46 COS13_R[3:0], COS14_R[3:0],// write_data(0x33); //47 COS15_R[3:0], COS16_R[3:0],// write_data(0x88); //48 COS17_R[3:0], COS18_R[3:0],// write_data(0xFF); //49 COS19_R[3:0], COS20_R[3:0],// write_data(0x13); //50 COS21_R[3:0], COS22_R[3:0],// write_data(0x00); //51 TCONOPTION write_data(0x00); //52 OPTION write_data(0x00); //53 OTPION write_data(0x00); //54 OPTION write_data(0x00); //55 CHR2 write_data(0x00); //56 CON2 write_data(0x00); //57 COFF2 write_data(0x00); //58 CHP2,CCP2 write_data(0x00); //59 CKS 21 20 19 18 17 16 write_data(0x00); //60 CKS 15 14 13 12 11 10 9 8 write_data(0x00); //61 CKS 7~0 write_data(0x00); //62 COFF[7:6] CON[5:4] SPOFF[3:2] SPON[1:0] write_data(0x00); //63 COFF2[7:6] CON2[5:4] - - - - write_command(0xEA); /// Set GIP2 write_data(0x00); //1 ys2_sel[1:0] write_data(0x1A); //2 user_gip_gate1[7:0] write_data(0x00); //3 ck_all_on_width1[5:0] write_data(0x00); //4 ck_all_on_width2[5:0] write_data(0x00); //5 ck_all_on_width3[5:0] write_data(0x00); //6 ys_flag_period[7:0] write_data(0x02); //7 ys_2 write_data(0x00); //8 user_gip_gate1_2[7:0] write_data(0x00); //9 ck_all_on_width1_2[5:0] write_data(0x00); //10 ck_all_on_width2_2[5:0] write_data(0x00); //11 ck_all_on_width3_2[5:0] write_data(0x00); //12 ys_flag_period_2[7:0] write_data(0x8F); //29 COS1_L[3:0], COS2_L[3:0] ,// X/X write_data(0xF8); //30 COS3_L[3:0], COS4_L[3:0] ,// X/X write_data(0x88); //31 COS5_L[3:0], COS6_L[3:0] ,// write_data(0x85); //32 COS7_L[3:0], COS8_L[3:0] ,// write_data(0x33); //33 COS9_L[3:0], COS10_L[3:0],// write_data(0x11); //34 COS11_L[3:0], COS12_L[3:0],// write_data(0x77); //35 COS13_L[3:0], COS14_L[3:0],// write_data(0x55); //36 COS15_L[3:0], COS16_L[3:0],// write_data(0x88); //37 COS17_L[3:0], COS18_L[3:0],// write_data(0xFF); //38 COS19_L[3:0], COS20_L[3:0],// write_data(0x31); //39 COS21_L[3:0], COS22_L[3:0],// XXX /XXX write_data(0x8F); //40 COS1_R[3:0], COS2_R[3:0] ,// X/X write_data(0xF8); //41 COS3_R[3:0], COS4_R[3:0] ,// X/X write_data(0x88); //42 COS5_R[3:0], COS6_R[3:0] ,// CLK4/CLK4 write_data(0x84); //43 COS7_R[3:0], COS8_R[3:0] ,// CLK2/CLK2 write_data(0x22); //44 COS9_R[3:0], COS10_R[3:0],// CLK8/CLK8 write_data(0x00); //45 COS11_R[3:0], COS12_R[3:0],// CLK6/CLK6 write_data(0x66); //46 COS13_R[3:0], COS14_R[3:0],// VGL/VGL write_data(0x44); //47 COS15_R[3:0], COS16_R[3:0],// STV2/VSD write_data(0x88); //48 COS17_R[3:0], COS18_R[3:0],// VDS/STV4 write_data(0xFF); //49 COS19_R[3:0], COS20_R[3:0],// GCH/GCL F8 write_data(0x20); //50 COS21_R[3:0], COS22_R[3:0],// XXX /XXX write_data(0x23); //35 EQOPT , EQ_SEL write_data(0x00); //36 EQ_DELAY[7:0] write_data(0x00); //37 EQ_DELAY_HSYNC [3:0] write_data(0x01); //38 HSYNC_TO_CL1_CNT9[8] write_data(0x02); //39 HSYNC_TO_CL1_CNT9[7:0] write_data(0x00); //40 HIZ_L write_data(0x00); //41 HIZ_R write_data(0x00); //42 CKS_GS[21:16] write_data(0x00); //43 CKS_GS[15:8] write_data(0x00); //44 CKS_GS[7:0] write_data(0x00); //45 CK_MSB_EN[21:16] write_data(0x00); //46 CK_MSB_EN[15:8] write_data(0x00); //47 CK_MSB_EN[7:0] write_data(0x00); //48 CK_MSB_EN_GS[21:16] write_data(0x00); //49 CK_MSB_EN_GS[15:8] write_data(0x00); //50 CK_MSB_EN_GS[7:0] write_data(0x00); //51 SHR2[11:8] write_data(0x00); //52 SHR2[7:0] write_data(0x00); //53 SHR2_1[3:0] SHR2_2 write_data(0x00); //54 SHR2_3[3:0] write_data(0x40); //55 SHP1[3:0] write_data(0xA1); //56 SPON1[7:0] write_data(0x80); //57 SPOFF1[7:0] write_data(0x00); //58 SHP2[3:0] write_data(0x00); //59 SPON2[7:0] write_data(0x00); //60 SPOFF2[7:0] write_data(0x00); //61 SPOFF2[9:8]/SPON2[9:8]/SPOFF1[9:8]/SPON1[9:8] write_command(0x11); ////Sleep Out delay(250); write_command(0x29); ///Display On delay(50); } //******************************************* void EnterSleep (void) { write_command(0x28); delay(10); write_command(0x10); } //********************************************************* void ExitSleep (void) { write_command(0x11); delay(120); write_command(0x29); }