RGB Signals and Timing Diagrams
The RGB interface drives the display by sending 16, 18, or 24-bits of RGB data through parallel lines. This data is then mapped by control signals to specify where and when these pixels should be displayed. The common control signals are HSYNC, VSYNC, DCLK, and DE and can be unique to each display. The timing parameters and diagrams for these signals can be found in the data sheet of the display. This note will describe how to read and calculate the necessary timing information from the display’s data sheet.
For this example we describe the timing parameters for the display E35RG83224LW2M250-C. This display offers a 16, 18 or 24-bit RGB interface. The display has a resolution of 320×240 pixels and that are arranged in and RGB vertical stripe. Additionally, this display has a color depth of up to 16.7M colors. For more information of this display consult the data sheet.
The 24-bit parallel RGB interface can be used in advanced applications with high speeds such as displaying video. The RGB data is sent through the 24 parallel data lines per one pixel. This data is then synced to the display through the control lines HYSYN, VSYNC, DE and DCLK. These signals have are described in the following table.
Each of these signals plays an important role in sending RGB data to each of the pixels on the display. For a 24-bit parallel RGB interface, there will typically be 24 data lines transmitting up to 24-btis every DCLK pulse. Starting at the very first pixel on the display the data is processed in the following way.
The VSYNC sends a sync signal followed by a brief buffering period called the vertical back porch. The front and back porches are used to specify the active area that will be visible on the display. Beginning at the first row, the HSYNC signal will be pulsed for each horizontal column on the display. During this period the RGB data is transmitted each DCLK and confirmed by the DE signal that the data is valid and within the HSYNC active area. This process is then repeated for every vertical row on the display. The following diagram elaborates the sequence of events.
In some RGB display controllers there will be an option between DE mode and HV. The only difference between these two interfaces is that HV mode does not have the added Data Enable signal. The DE signal is used as an additional verification step to indicate valid data being transferred. Both of interfaces will require HSYNC, VSYNC and a clocking signal.
In continuation of this example, the specific timing values will need to be evaluated from the data sheet and controller spec sheet. The IC display controller in this example is the HX8238-D. The timing parameters will be needed to function the display and will also be used to calculate the required memory allocation and processing speed of the external CPU. The necessary values are as follows:
From this data we can calculate the following parameters:
Horizontal Line: HBP + HFP + HDISP = 68 + 20 + 320 = 408 DCLK/Line
Vertical Frame: VBP + VFP + VDISP = 18 + 4 + 240 = 262 Lines/Frame
Full Frame: 408 DCLK/Line * 262 Lines/Frame = 106,896 DCLK’s/Frame
Frame Rate at DCLK = 6.5MHz clock speed: 6.5MHz/106,896 = 60.8 Hz
This Frame Rate is the median value of the oscillation frequency required to refresh the display in order to maintain an image. The minimum and maximum values can be calculated similarly from the data.
Maximum DCLK frequency is given at 10MHz. Therefor maximum frame rate achievable by the controller is 10MHz/157,500 = 93.5 Hz.
The memory needed to store this data in order to refresh the display is called the frame buffer. The frame buffer is dependent on the size of the display and the color depth chosen. For example, a 16-bpp color depth (RGB-565) for this display would need a frame buffer size of 240 x 320 x 16bpp = 1,228,800 bits or 153.6kB of memory per frame.
Display refresh rate can impact CPU performance for very large displays. It is important to take into consideration the memory needed for the frame buffer and the capabilities of the external CPU. Performance issues can be minimized by increasing the number or communication buses, caching the CPU and efficiently allocating internal memory.
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